This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-295068 filed on Sep. 27, 2000, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a method of and a program of processing design pattern data of a semiconductor integrated circuit such as an LSI. In particular, the present invention relates to checking LSI patterns by design rules, preparing mask writing data, and correcting optical or electron beam proximity effect.
2. Description of the Related Art
LSIs are getting denser and finer to increase the amount of design pattern data involved. To minimize design pattern data, hierarchical processing is imperative.
A hierarchical processing technique to correct a proximity effect is disclosed in Japanese Patent Publication No. 03-80525 xe2x80x9cCorrecting Method for Proximity Effectxe2x80x9d (first related art).
The hierarchical processing technique of the first related art will be explained with reference to FIG. 1. A higher-level cell A (901) contains a lower-level cell B (902). Double frame areas defined by frames A (911) and B (912) are prepared inside the boundary of the cell B.
When processing the cell B to correct a proximity effect, an inside area of the frame 911 is set as a proximity effect correction area and an area between the boundary of the cell B and the frame 911 is set as a reference area.
When processing the cell A to correct a proximity effect, the area between the cell B and the frame 911 is added as a proximity effect correction area, and an area between the frames 911 and 912 is set as a reference area.
The reason why a reference area defined by frames is set inside or outside a proximity effect correction area is to cope with the influence of back scattering electrons from the reference area. Accordingly, the size of a reference area defined by frames is dependent on a scattering length of back scattering electrons.
A hierarchical processing technique to check patterns by design rules is disclosed in Todd J. Wagner of Intel Corp., xe2x80x9cHierarchical Layout Verification,xe2x80x9d 21st Design Automation Conference, pp. 484-489, 1984 (second related art). This hierarchical processing technique finds space and width violations based on design rules and is substantially equal to the technique of FIG. 1. The second related art determines the width of a frame area according to spaces and widths to check.
A hierarchical processing technique to prepare mask writing data is disclosed in Japanese Patent Publication No. 09-260253 xe2x80x9cCharged Beam Image Sensing Data Forming Methodxe2x80x9d (third related art). This technique flattens each lower-level cell whose size is below a threshold into a higher level and prepares data to draw a mask. The third related art flattens an array of lower-level cells into a higher level if the area of the array is small, or if the number of cells in the array is small.
A method according to an embodiment of the present invention includes determining whether or not there are lower-level cells whose individual size is equal to or below a threshold, and if there are such lower-level cells, collecting the lower-level cells to define a new cell whose size is greater than the threshold, and replacing the lower-level cells with the new cell.